(1) Field of the Invention
This invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of reducing noise on power lines with a bypass capacitor.
(2) Description of the Related Art
Some semiconductor devices contain bypass capacitors to avoid malfunctions of the internal circuits caused by instability of power sources and high-frequency noise on power lines. For such a bypass capacitor, first and second wiring layers which are multilayered are provided. The first and second wiring layers are used for first and second power lines, respectively. One of these lines is placed on the other, thereby creating a capacitance. As a result, the bypass capacitor is formed in the semiconductor device (for example, refer to columns [0019 ]–[0022] and FIG. 1 in Japanese Patent Laid Open No. 9-64284).
To avoid common mode noise on a digital multilayer board, a bypass capacitor is inserted between a circuit and a power source. High frequency current necessary for circuit switching is supplied through power lines in wiring layers. Therefore, if a bypass capacitor is not installed, voltage varies due to inductance between a power line and a circuit, resulting in generating pulse noise. To minimize the inductance as much as possible, a bypass capacitor is installed close to the circuit. That is, by temporarily accumulating direct current in the bypass capacitor, necessary high frequency current is supplied to the circuit stability. This suppresses the variation of the power source current which causes high frequency noise, resulting in reducing the common mode noise on the digital multilayer board.
FIG. 3 is a cross-sectional view of a conventional semiconductor device.
As shown in FIG. 3, in the semiconductor device, two-layered power lines 103a and 103b being connected to each other via a contact 102 and two-layered power lines 105a and 105b being connected to each other via a contact 104 are arranged above a bypass capacitor 101. In addition, a NAND gate 106 is arranged above the power lines 103a and 105a. 
The bypass capacitor 101 is composed of a MOS transistor. The bypass capacitor 101 is composed of a P-type semiconductor substrate 101a, two N-type regions 101b and 101c formed on the substrate 101a, and a gate electrode 101d on the N-type regions 101b and 101c with a gate insulating film inserted therebetween. The gate electrode 101d and one of the N-type regions 101b and 101c serve as the terminals of the bypass capacitor 101.
The power lines 103a and 103b being connected to each other with the contact 102 are connected to one electrode of the power source. The lower-layered power line 103b is connected to the N-type region 101b of the bypass capacitor 101. The power lines 105a and 105b being connected to each other with the contact 104 are connected to the other electrode of the power source. The lower-layered power line 105b is connected to the gate electrode 101d of the bypass capacitor 101.
The NAND gate 106 operates by receiving power through the power lines 103a and 105a. The bypass capacitor 101 is installed close to the NAND gate 106 so as to effectively eliminate noise on the power lines 103a, 103b, 105a, and 105b. 
FIG. 4 is a plan view of another conventional semiconductor device.
As shown in FIG. 4, a semiconductor tip 112 is provided in a package 111. Arranged on the semiconductor tip 112 are bypass capacitors 113a and 113b, I/O cells 114a and 114b, power lines 115a and 115b, and pads 116a and 116b. Leads 117a and 117b are provided in the package 111. The pads 116a and 116b and the leads 117a and 117b are connected to each other with wires 118a and 118b by bonding.
The power lines have a two-layer wiring structure. FIG. 4 shows only upper-layered power lines 115a and 115b (lower-layered power lines are hidden by the upper-layered power lines 115a and 115b). The I/O cells 114a and 114b are connected to the lower-layered power lines to receive power.
Signals from the I/O cells 114a and 114b are output to the leads 117a and 117b through the pads 116a and 116b and the wires 118a and 118b. Signals entered into the leads 117a and 117b are input to the I/O cells 114a and 114b through the wires 118a and 118b and the pads 116a and 116b. 
The I/O cells 114a and 114b receive power through the power lines 115a and 115b to amplify signals. The bypass capacitors 113a and 113b are installed close the I/O cells 114a and 114b so as to effectively eliminate noise on the power lines 115a and 115b. 